The present invention relates generally to testing and troubleshooting microprocessor-based electronic systems, and in particular to testing and troubleshooting such microprocessor-based systems using memory emulation techniques.
With increasingly complex microprocessor-based systems presently being implemented in a wide variety of consumer and industrial products, automation of test and troubleshooting procedures is virtually a necessity. A number of test techniques, such as signature analysis, logic level detection, frequency and event counting, pulsing and emulative testing, are well known and have been used for many years. In particular, emulative testers, so called because they emulate the behavior of kernel-related devices, are popular for functional testing and fault isolation in microprocessor-based boards or systems because in the first place they test the system from the inside out, and in the second place they can test a system in which the kernel is dead.
One such emulative tester is a microprocessor emulator described in U.S. Pat. No. 4,455,654 issued to K. S. Bhaskar et al. and assigned to John Fluke Mfg. Co., Inc. Here, a test system, which itself is a microprocessor-based system, is connected in place of a microprocessor in a unit under test (UUT). The Bhaskar et al. test system operates in a bus-access mode wherein single cycles of bus accesses are made and acted upon before making another. That is, for one bus cycle, the test system microprocessor is switched into signal communication with the UUT bus to perform a read or write operation. Then the test system microprocessor is switched over to the test system internal circuitry to generate another read or write command with a new address, or deal with information read from the UUT's memory. The bus switching required to effect single cycles of bus accesses is becoming a limitation of microprocessor emulators such as that described by Bhaskar et al. as microprocessor-based systems become more complex and operate at higher speeds. Suitable bus switches for newer microprocessor-based UUT's, e.g., for 80386 systems, are non-trivial and difficult to design. Accordingly, it would be desirable to provide a different method by which a test system can be connected into the kernel of a UUT to carry out diagnostic test procedures.
Another type of emulative testing that has been considered is ROM (Read-Only Memory) emulation because ROMs are in direct communication with the UUT system bus and also because the pin configurations of ROMs are relatively simple so that interface connectors are easily designed. Historically, ROM emulators have been used for software development or to verify that hardware is working. ROM emulators historically have not been used for troubleshooting or fault detection because no sync signal is available to synchronize test equipment with test results, and further because test equipment could not directly retrieve test information from the UUT ROM socket. A partial solution to this problem is described in U.S. Pat. No. 4,691,316, wherein a ROM emulator is connected to a ROM I/O port of a UUT and the results of diagnostic test results are read over the UUT address bus in the form of encoded address information, which are subsequently decoded and latched in the ROM emulator. It is to be pointed out, however, that this system does not provide complete fault diagnosis of a UUT kernel and is limited to what can be communicated over an address bus. Moreover, the trend in microprocessor systems is to increase the random-access portion of memory while reducing the read-only portion. It is conceivable that eventually ROM could be eliminated so that the use of ROM emulators would be obviated.